The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically to a semiconductor device characterized by a junction structure between an adhesion improving layer and a capacitor dielectric film used in a storage capacitor formed in a DRAM (Dynamic Random Access Memory) or an FeRAM (Ferroelectric RAM), and a method for fabricating the same.
Recently, as semiconductor devices are more highly integrated and have larger capacities, design rules (line/space) have become increasingly precise. Accordingly, the semiconductor devices, e.g., DRAMs (Dynamic Random Access Memories) have widths of the wiring layers decreased, and the contact plugs connecting the storage nodes which are to be the lower connection electrodes of the storage capacitors to the source regions have smaller diameters.
Such the DRAM comprises cell regions each including one transistor and one storage capacitor, for storing 1-bit information. The storage capacitor comprises a lower electrode called a storage node, an upper electrode called a cell plate, and a capacitor dielectric film sandwiched between the upper and the lower electrodes.
In the conventional DRAM, an electrode material of the storage node and the cell plate is doped polycrystalline silicon, and the capacitor dielectric film is ON film (a composite film of SiO2 and Si3N4) formed by thermally oxidizing the surface of a thin CVD nitride film.
The storage node is formed in a projected electrode structure to use as a capacitor not only the upper surface but also the side surfaces, whereby a sufficient capacitance can be obtained for a limited space (floor area). This has a background that the capacitance cannot be lowered below a prescribed capacitance, e.g., about 30 fF in order to cope with alpha radiation and decrease of the source voltage.
In addition, DRAMs have been developed with the integration improved by about 4 times every three years, i.e., the micronization improved; the projected structure of the storage capacitor, i.e., the projected structure of the storage node tends to become higher and higher so that a sufficient surface area can be ensured for a decreased capacitor floor area.
However, as the storage capacitor structure becomes higher, a height difference from the peripheral circuit region becomes larger. This resultantly causes a problem that the wiring layer becomes thin at the step, and the wiring becomes less reliable, and, in the exposing step, a problem of a depth of focus that the higher region and the lower region cannot be simultaneously focused.
On the other hand, although the above-described problems can be solved by planarizing with an insulation film to be equalized the height with the higher surface, there occur additional problems that contact holes in the peripheral circuit regions become deeper, making the etching difficult and that the contact holes of such high aspect ratio cannot be filled with a metal electrode material of low resistance.
Then, a material having a higher dielectric constant, i.e., a high dielectric constant film is required in place of the conventional ON film (a composite film of SiO2 and Si3N4) as the capacitor dielectric film. Such the high dielectric constant film is used to thereby obtain a higher capacitance per a unit area. Studies of obtaining a required capacitance without increasing a height of the projected structure of the storage capacitor are made. This produces an advantage of simplifying steps of the fabrication.
As such the high dielectric constant film, the use of Ta2O5 film, SBT (SrBi2Ta2O9) film, BST ((Ba,Sr)TiO3) film, etc. are studied. These high dielectric constant materials are basically oxides, and have a problem that when these films are deprived of oxygen, these films become conductive, and leak current tends to flow in the films.
DRAMs store information in charges stored in the storage capacitors. Seriously, increase of leak current means extinction of information stored in the DRAMS.
The storage node and the cell plate of the conventional storage capacitor are formed of polycrystalline silicon. Polycrystalline silicon can be easily deprived of oxygen. In using a high dielectric constant film as the capacitor dielectric film, it is vital to use an electrode material which take place of polycrystalline silicon.
An electrode material suitable for such the high dielectric constant film must satisfy the following (1) to (6) requirements:
(1) Oxygen defect which is a cause for depriving a high dielectric constant film of oxygen to cause leak current does not take place.
(2) An electrode material itself does not diffuse in the high dielectric constant film to cause deterioration of the high dielectric constant film.
(3) An electrode material is able to withstand high-temperature annealing for crystallizing the high dielectric constant film.
(4) The electrode material can be easily etched.
(5) An electrode material has a resistance as low as possible.
(6) An electrode material has good adhesion with a base insulation film, so that peeling does not take place after heat treatment.
However, it is very difficult to satisfy all the six requirements from (1) to (6), and no electrode material which satisfy all of the requirements has been so far found. Electrode materials, for example, Ru (Ruthenium) and RuO (Ruthenium Oxide), can satisfy, to some extent, the requirements (1) to (5) but does not satisfy the requirement (6).
That is, a Ru film and a RuO film have a defect that they tend to peel from the insulation film.
Then, in order to solve such defect of the peeling of these electrode films, which is their only one defect, it is considered to provide below such electrode materials an adhesion improving layer having good adhesion with the base insulation film for the prevention of the pealing of the electrode materials. As such the adhesion improving layer, TiN, WN, and Ta, etc. are prospective.
Here, with reference to FIGS. 38A and 38B, the storage capacitor of the conventional DRAM using Ru as the storage node and having the adhesion improving layer will be explained.
FIG. 38B is a plan view of the DRAM at the time that a lower plug 75 of the DRAM is formed. FIG. 38A is a sectional view of the DRAM. In FIG. 38A, the layer structure up to a first inter-layer insulation film 69 is a sectional view along the one-dot chain line B-Bxe2x80x2 in FIG. 38B, the layer structure from a second inter-layer insulation film 72 to a third inter-layer insulation film 74 is a sectional view along the one-dot line A-Axe2x80x2 in FIG. 38B, and the layer structure thereabove is a sectional view again along the one-dot chain line B-Bxe2x80x2 in FIG. 38B. In FIG. 38A, the layer structure below the third inter-layer insulation film is represented conveniently by A-Axe2x80x2 to simplify the showing.
In FIG. 38A, for convenience, a bit line 73 is shown, shorted to the lower plug 75, but they are positionally isolated from each other as shown in FIG. 38B.
Reference will be made to FIGS. 38A and 38B.
First, a device isolation oxide film 62 is formed by selective oxidation in a prescribed region of a p-type silicon substrate 61. Then, the exposed surface of the p-type silicon substrate 61 surrounded by the device isolation oxide film 62 is thermally oxidized to form a gate oxide film 63. Next, a non-doped polycrystalline silicon film is deposited, and an impurity, such as P (phosphorus) or others, is ion-implanted. Then, the polycrystalline silicon layer is etched into a prescribed pattern to form gate electrodes 64 and word lines 65, which are extensions of the gate electrodes 64.
Actually, an SiO2 film or an Si3N4 film as a protection film is provided by CVD method on the gate electrodes 64.
Then, as the gate electrodes 64 as a mask, an impurity, such as As (arsenic), P or others, is ionimplanted to form an n+-type drain region 67 and an n+-type source region 68. Then, an SiO2 film is deposited on the entire surface by CVD method and is subjected to anisotropic etching to form sidewalls 66.
Instead, in the above-described ion implanting step, As ions are implanted to form an LDD (Lightly Doped Drain) in a shallow nxe2x88x92-type region, and the sidewalls 66 are formed. Then, P ions are implanted to form the n+-type drain region 67 and the n+-type source region 68.
Then, an SiO2 film is deposited on the entire surface by CVD method to form the first inter-layer insulation film 69. A via hole for the n+-type drain region 67 and the n+-type source region 68 is formed. A TiN (titanium nitride) film to be a barrier metal and next a W (tungsten) film, etc. are deposited by CVD method or sputtering method, and are polished by CMP (Chemical Mechanical Polishing) method to form contact plugs 70, 71 with the W film, etc. buried in.
Next, an SiO2 film is deposited on the entire surface by CVD method to form the second inter-layer insulation film 72, and a via hole for the contact plug 70 is formed. Then, a doped polycrystalline silicon film, a WSi2 film, etc. are deposited on the entire surface by LPCVD (Low Pressure Chemical Vapor Deposition) method and then patterned to form the bit line 73.
Next, again an SiO2 film is deposited on the entire surface by CVD method to form the third inter-layer insulation film 74, and a via hole for the contact plug 71 is formed. Then again a W film is deposited on the entire surface by LPCVD method and polished by CMP method to form the lower plug 75 buried in the via hole.
A TiN film and an Ru film are sequentially deposited on the entire surface by sputtering and then etched to form the adhesion improving layer 76 and a storage node 77 in a projected shape. Then, again a Ta2O5 film and an Ru film are sequentially deposited by sputtering and etched into a prescribed shape to form the capacitor dielectric film 78 and the cell plate 70. Thus, a basic structure of the DRAM is completed.
In this case, the storage capacitor is constituted by the storage node 77, the cell plate 79, and the capacitor dielectric film 78 sandwiched by both, and is electrically connected to the n+-type source region 68 via the adhesion improving layer 76, the lower plug 75, and to the contact plug 71.
However, in the storage capacitor using such the adhesion improving layer 76, the adhesion improving layer 76, and the capacitor dielectric film 78 of the Ta2O5 film contact directly to each other at both ends of the adhesion improving layer 76 circled by the dotted lines. At these ends, oxygen in the Ta2O5 film diffuses in the TiN film forming the adhesion improving layer 76 to cause oxygen defect in the Ta2O5 film. As a result, a problem of deterioration of the capacitor dielectric film 78 is caused.
That is, the adhesion improving layer 76 of TiN film, etc. satisfy the requirements (4) to (6) out of the requirements (1) to (6) but does not satisfy the requirements (1) to (3). Accordingly, there occurs the problem that the high dielectric constant film at the sidewall of the adhesion improving layer 76 is degraded, and leak current undesirably flows.
In order to solve this problem of deterioration of the high dielectric constant film on the sidewall of the adhesion improving layer 76, it is considered to from the adhesion improving layer 76 in a buried structure. Such improved storage capacitor will be explained with reference to FIGS. 39A and 39B.
FIG. 39A shows a sectional view of the same part as FIG. 38A. FIG. 39A, however, omits, the structure on the side of p-type silicon substrate 61, and another transistor commonly using an n+-type drain region 67 so as to simplify the explanation.
In FIG. 39A, the view on the right side is a view showing the positional relationship between a storage node 77 and the adhesion improving layer 76.
Reference is made to FIG. 39A.
The structure up to the third inter-layer insulation film 74 is formed in completely the same way as in FIG. 38A. Then, a via hole arriving at the contact plug 71 is formed and then filled with the lower plug 76 of W film by CMP. Then, the lower plug 75 is over-etched to form a cavity in the via hole. Then, a TiN film is deposited and polished by CMP method to be buried as the adhesion improving layer 76 in the cavity.
Hereafter, an Ru is deposited in the same way as in FIG. 38A and is etched into a prescribed shape to form the storage node 77 in a projected shape. Next, again, a Ta2O5 film and an Ru film are sequentially deposited by sputtering method and etched into a prescribed shape to form a capacitor dielectric film 78 and a cell plate 79. Thus, a basic structure of the DRAM is completed.
In the case that the adhesion improving layer 76 is thus buried, the Ta2O5 film forming the capacitor dielectric film 78 is kept out of direct contact with the adhesion improving layer 76, whereby deterioration of the capacitor dielectric film 78 never takes place.
However, as the integration of the DRAM is improved, an alignment allowance between the storage node 77 and the adhesion improving layer 76 is so small that, in view of the alignment precision of the current exposure systems, it is actually impossible to prevent, without failure, the adhesion improving layer 78, accordingly the lower plug 75, from appearing beyond the storage node 77. This causes additional problems. These problems will be explained with reference to FIG. 39B.
FIG. 39B is a sectional view of the same part as FIG. 39A.
Reference is made to FIG. 39B.
As shown by the view on the right side in FIG. 39B, in the case that the lower plug 75, accordingly the adhesion improving layer 76, appears beyond the storage node 77, the adhesion improving layer 76 and the capacitor dielectric film 78 contact directly to each other in the part circled by the broken line in the view on the left side in FIG. 39B. At this part, the deterioration of the capacitor dielectric film 78 takes place, causing leak current.
In addition to an area of the adhesion improving layer decreased by the buried structure, when such disalignment takes place, an area of the contact between the adhesion improving layer 76 and the storage node 77 becomes smaller, which causes an additional problem of the peeling of the storage node 77.
An object of the present invention is to prevent the peeling of the storage node and occurrence of leak current even when disalignment takes place between the lower plug and the storage node.
FIGS. 1A and 1B are views explaining a principle constitution of the invention of the present application. With reference to FIG. 1, the present invention will be summarized.
FIG. 1A is an enlarged sectional view of a major part of a capacitor in a case that the disalignment between a lower connection electrode 1 buried in an inter-layer insulation film 2 and a lower electrode 4, e.g., disalignment between the lower plug and the storage node, is absent. FIG. 1B is an enlarged sectional view of the major part in a case that the disalignment is present.
Reference is made to FIGS. 1A and 1B.
(1) The semiconductor device according to the present invention comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3, and at least a portion of the gap is left as a cavity 7, whereby the upper electrode 6 and the adhesion improving layer 3 are insulated from each other by the cavity 7.
The upper electrode 6, typically the cell plate is thus insulated from the adhesion improving layer 3 through the cavity 7, whereby even if the capacitor dielectric film 5 and the adhesion improving layer 3 should be contiguous, generation of leak current can be prevented. A retention time of information in micronized DRAMs can be much longer.
(2) In the above-described semiconductor device according to the present invention described above in item (1), the sidewall of the adhesion improving layer 3 is contiguous to the capacitor dielectric film 5, and the cavity 7 is surrounded by the capacitor dielectric film 5 and the upper electrode 6.
The upper electrode 6 and the adhesion improving layer 3 are thus insulatively isolated from each other by the cavity 7 as shown in item (1), whereby even when the sidewall of the adhesion improving layer 3 and the capacitor dielectric film 5 are contiguous to thereby deteriorate the capacitor dielectric film 5 at the contiguous part, no voltage is effectively applied to the contiguous part, and increase of leak current can be restrained.
(3) In the semiconductor device according to the present invention described above in item (1), a part of the gap is filled with the capacitor dielectric film 5, and the cavity 7 is formed between the sidewall of the adhesion improving layer 3 and the capacitor dielectric film 5.
The upper electrode 6 and the adhesion improving layer 3 are insulated by the cavity 7 as shown in item (1), and it is possible that the gap is made narrower, and the gap is partially filled with the capacitor dielectric film 5.
(4) In the semiconductor device according to the present invention described above in item (1), a whole of the gap is the cavity 7, and the cavity 7 is formed between the sidewall of the adhesion improving layer 3 and the capacitor dielectric film 5.
The upper electrode 6 and the adhesion improving layer 3 are insulated from each other by the cavity 7 as shown in item (1), and it is possible that the gap is made narrower, and the entire gap is the cavity 7.
(5) The semiconductor device according to the present invention comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3, and the gap is completely filled with the capacitor dielectric film 5.
When the gap is thus completely filled with the capacitor dielectric film 5, a voltage V is applied through the buried capacitor dielectric film 5 of a thickness D, whereby an electric field E (=V/D) is much mitigated, and no leak current does increase even at the contiguous part where the adhesion improving layer 3 and the capacitor dielectric film 5 are contiguous to each other.
(6) The semiconductor device according to the present invention comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3, and the gap is completely filled with an insulation film which is different from the capacitor dielectric film 5.
In the case that the gap is thus completely filled with a deposited insulation film, such as CVD-SiO2 film or others, a voltage V is applied through the buried capacitor dielectric film 5 of a thickness D, whereby an electric field E (=V/D) is much mitigated. Furthermore, the adhesion improving layer 3 and the capacitor dielectric film 5 are not contiguous directly to each other, whereby the capacitor dielectric film 5 does not deteriorate.
(7) The semiconductor device according to the present invention comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3, and the gap is completely filled with a self-oxidized film or a self-nitridized film of the lower electrode 4.
In this case, an self-oxide film or a self-nitride film of the lower electrode must be conductive.
Also in the case the gap is thus completely filled with a self-oxide film or a self-nitride film of the lower electrode 4, a voltage V is applied through the thick self-oxide or self-nitride film of a thickness D, whereby an electric field E (=V/D) is much mitigated. In addition, the adhesion improving layer 3 and the capacitor dielectric film 5 are not contiguous directly to each other, whereby the capacitor dielectric film 5 does not deteriorate.
(8) The semiconductor device according to the present invention comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a self-oxidized film of the adhesion improving layer 3 is formed on the sidewall of the adhesion improving layer 3, whereby the adhesion improving layer 3 and the capacitor dielectric film 5 are isolated from each other by the self-oxidized film of the adhesion improving layer 3.
A self-oxide film of the adhesion improving layer is thus provided on the sidewall of the adhesion improving layer 3, and the adhesion improving layer 3 and the capacitor dielectric film 5 are not contiguous directly to each other, whereby the capacitor dielectric film does not deteriorate. In addition, an electric filed is mitigated by an thickness of the self-oxide film of the adhesion improving layer 3. In this case, it is not necessary to define the gap on the sidewall of the adhesion improving layer 3.
(9) The semiconductor device according to the present invention comprises: a lower contact electrode 1; a capacitor including a lower electrode 4 in a projected structure formed on the lower contact electrode 1, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5; and an adhesion improving layer 3 being contiguous to the lower electrode 4 and the lower contact electrode 1, in which the adhesion improving layer 3 is formed, covering at least a sidewall of the lower contact electrode 1, a gap is formed on a sidewall of the adhesion improving layer 3 at a part where the lower electrode 4 and the lower contact electrode 1 do not disalign with each other, a gap is formed on the sidewall of the lower contact electrode 1 at a portion of a part where the lower electrode 4 and the lower contact electrode 1 disalign with each other, and each said gaps is left partially as a cavity 7, whereby the upper electrode 6 and the adhesion improving layer 3 are insulated from each other by the cavity 7.
At least the side surface of the lower contact electrode 1 is thus covered with the adhesion improving layer 3, whereby peeling of the lower contact electrode 1 can be effectively prevented. This leads to the prevention of peeling of the lower electrode 4. In this case as well, the upper electrode 6 and the adhesion improving layer 3 are insulated from each other by the cavity 7, whereby generation of leak current can be prevented.
(10) In the semiconductor device according to the present invention described above in item (9), the adhesion improving layer 3 and a capacitor dielectric film 5 are contiguous to each other, and the cavity 7 is surrounded by the capacitor dielectric film 5 and the upper electrode 6.
(11) In the semiconductor device according to the present invention described above in item (9), the gap is partially filled with the capacitor dielectric film 5, and the cavity 7 is formed between the adhesion improving layer 3 and the capacitor dielectric film 5.
(12) In the semiconductor device according to the present invention described above in item (10), a whole of the gap is the cavity 7, and the cavity 7 is formed between the adhesion improving layer 3 and the capacitor dielectric film 5.
(13) The semiconductor device according to the present invention comprises: a lower contact electrode 1; a capacitor including a lower electrode 4 in a projected structure formed on the lower contact electrode 1, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5; and an adhesion improving layer 3 being contiguous to a lower electrode 4 and a lower contact electrode 1, in which the adhesion improving layer 3 is formed, covering at least a sidewall of the lower contact electrode 1, a gap is formed on a sidewall of the adhesion improving layer 3 at a part where the lower electrode 4 and the lower contact electrode 1 do not disalign with each other, a gap is formed on a sidewall of the lower contact electrode 1 at a portion of a part where the lower electrode 4 and the lower contact electrode 1 disalign with each other, and each said gaps is completely filled with a capacitor dielectric film 5.
(14) The semiconductor device according to the present invention comprises: a lower contact electrode 1; a capacitor including a lower electrode 4 in a projected structure formed on the lower contact electrode 1, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5; and an adhesion improving layer 3 being contiguous to a lower electrode 4 and a lower contact electrode 1, in which the adhesion improving layer 3 is formed, covering at least a sidewall of the lower contact electrode 1, a gap is formed on a sidewall of the adhesion improving layer 3 at a part where the lower electrode 4 and the lower contact electrode 1 do not disalign with each other, a gap is formed on a sidewall of the lower contact electrode 1 at a portion of a part where the lower electrode 4 and the lower contact electrode 1 disalign with each other, and each said gaps is completely filled with an insulation film which is different form the capacitor dielectric film 5.
(15) The semiconductor device according to the present invention comprises: a lower contact electrode 1; a capacitor including a lower electrode 4 in a projected structure formed on the lower contact electrode 1, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5; and an adhesion improving layer 3 being contiguous to a lower electrode 4 and a lower contact electrode 1, in which the adhesion improving layer 3 is formed, covering at least a sidewall of the lower contact electrode 1, a gap is formed on a sidewall of the adhesion improving layer 3 at a part where the lower electrode 4 and the lower contact electrode 1 do not disalign with each other, a gap is formed on a sidewall of the lower contact electrode 1 at a portion of a part where the lower electrode 4 and the lower contact electrode 1 disalign with each other, and each said gaps is completely filled with a self-oxidized film or a self-nitridized film of the lower electrode 4.
In the semiconductor device according to the present invention described above in items (10) to (15), the gap is defined on the sidewall of the lower contact electrode 1 at a portion of a part where the lower electrode 4 and the lower contact electrode 1 disaligned from each other. The gap is longitudinally defined. In this case as well, generation of leak current can be prevented by using the same constitution as stated in items (2) to (7).
(16) The semiconductor device according to the present invention comprises: a lower contact electrode 1; a capacitor including a lower electrode 4 in a projected structure formed on the lower contact electrode 1, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5; and an adhesion improving layer 3 being contiguous to a lower electrode 4 and a lower contact electrode 1, in which the adhesion improving layer 3 is formed, covering at least a sidewall of the lower contact electrode 1, a self-oxidized film of the adhesion improving layer is formed on a sidewall of the adhesion improving layer 3 at a part where the lower electrode 4 and the lower contact electrode 1 do not disalign with each other, and a self-oxidized film of the adhesion improving layer 3 is formed on a exposed portion of the adhesion improving layer 3 at a portion of a part where the lower electrode 4 and the lower contact electrode 1 disalign with each other, whereby the adhesion improving layer 3 and the capacitor dielectric film 5 are isolated from each other by the self-oxidized film of the adhesion improving layer 3.
Also in the case that at least the side surface of the lower contact electrode 1 is thus covered with the adhesion improving layer 3, an self-oxide film of the adhesion improving layer 3 is provided without defining the gap to thereby prevent generation of leak current.
(17) In the semiconductor device according to the present invention described above in any one of items (9) to (16), the lower contact electrode 1 and the lower electrode 4 are formed in one-piece with each other.
In the case that at least the side surface of the lower contact electrode 1 is thus covered with the adhesion improving layer 3, the lower contact electrode 1 and the lower electrode 4 may be formed in one-piece with each other. The step of forming an electrode material for burying the lower contact electrode 1, and the CMP step are not necessary.
The semiconductor device according to the present invention comprises: a lower contact electrode; a capacitor including a lower electrode in a projected structure formed on the lower contact electrode, a capacitor dielectric film formed on the lower electrode, and an upper electrode formed on the capacitor dielectric film; and an adhesion improving layer being contiguous to a lower electrode and a lower contact electrode, in which the adhesion improving layer is formed, covering at least a sidewall of the lower contact electrode, a gap is formed on a sidewall of the adhesion improving layer at a part where the lower electrode and the lower contact electrode do not disalign with each other, and a gap is formed on a sidewall of the lower contact electrode at a portion of a part where the lower electrode and the lower contact electrode disalign with each other.
In the above-described semiconductor device, it is preferable that each said gaps is completely filled with an insulation film which is different form the capacitor dielectric film.
In the above-described semiconductor device, it is preferable that each said gaps is completely filled with a self-oxidized film or a self-nitridized film of the lower electrode.
The semiconductor device according to the present invention comprises: a lower contact electrode; a capacitor including a lower electrode in a projected structure formed on the lower contact electrode, a capacitor dielectric film formed on the lower electrode, and an upper electrode formed on the capacitor dielectric film; and an adhesion improving layer being contiguous to a lower electrode and a lower contact electrode, in which the adhesion improving layer is formed, covering at least a sidewall of the lower contact electrode, a self-oxidized film of the adhesion improving layer is formed on a sidewall of the adhesion improving layer at a part where the lower electrode and the lower contact electrode do not disalign with each other, and a self-oxidized film of the adhesion improving layer is formed on a exposed portion of the adhesion improving layer at a portion of a part where the lower electrode and the lower contact electrode disalign with each other, whereby the adhesion improving layer and the capacitor dielectric film are isolated from each other by the self-oxidized film of the adhesion improving layer.
(18) The method for fabricating the semiconductor device according to the present invention includes the step of etching an adhesion improving layer 3 which is contiguous to a lower electrode 4 of a capacitor in a projected structure and a lower contact electrode 1, in which the adhesion improving layer 3 is excessively etched to form a gap, and then a capacitor dielectric film 5 covering the lower electrode 4 is formed.
The gap for insulating the upper electrode 6 and the adhesion improving layer 3 from each other can be formed simply and by self-alignment by excessively etching the adhesion improving layer 3.
(19) In the method for fabricating the semiconductor device according to the present invention described above in item (18), the adhesion improving layer 3 is formed to cover at least a sidewall of the lower contact electrode 1, a gap is formed on a sidewall of the adhesion improving layer 3 at a part where the lower electrode 4 and the lower contact electrode 1 disalign with each other, and a gap is formed on the sidewall of the lower contact electrode 1 at a portion of a part where the lower electrode 4 and the lower contact electrode 1 disalign with each other.
In the case that to prevent peeling of the lower contact electrode 1, the adhesion improving layer 3 is thus provided to cover at least the side surface of the lower contact electrode 1, the gap is defined on the sidewall of the lower contact electrode 1 at a portion of a part where the lower electrode 4 and the lower contact electrode 1 disaligned from each other, which makes no problem.
(20) The semiconductor device fabrication method according to the present invention comprises the steps of: forming an opening in an insulation film; forming an adhesion improving layer 3, covering at least a sidewall of the opening; depositing a conductive material, filling the opening; polishing or etching back the conductive material to form the lower contact electrode 1 and a lower electrode 4 buried in the opening, the lower contact electrode 1 and the lower electrode 4 being formed in one-piece; removing at least a part of the insulation film; etching the exposed adhesion improving layer 3 to form a gap on a sidewall of the lower contact electrode 1; and forming a capacitor dielectric film 5 covering the lower electrode 4.
The lower contact electrode 1 and the lower electrode 4 may be thus formed unseparable in one-piece by CMP. In this case as well, the adhesion improving layer 3 is excessively etched to define by self-alignment the gap on the sidewall of the lower contact electrode 1.
(21) The semiconductor device fabrication method according to the present invention comprises the steps of: etching an adhesion improving layer 3 contiguous to a lower electrode 4 of a capacitor in a projected structure and a lower contact electrode 1; oxidizing at least an exposed part of the adhesion improving layer 3 to form a self-oxidized film of the adhesion improving layer 3; and forming a capacitor dielectric film 5 covering the lower electrode 4.
In the case that a self-oxide film of the adhesion improving layer 3 is thus used, the excessive etching step for defining the gap is unnecessary. The steps can be simple.
(22) In the semiconductor device fabrication method according to the present invention described in item (21), the adhesion improving layer 3 is formed so as to cover at lest a sidewall of the lower contact electrode 1.
The adhesion improving layer 3 is thus provided to cover at least the side surface of the lower contact electrode 1, whereby peeling of the lower contact electrode 1 can be prevented, which leads to the prevention of peeling of the lower electrode 4.
(23) The semiconductor device fabrication method according to the present invention comprises the steps of: forming an opening in an insulation film; forming an adhesion improving layer 3, covering at least a sidewall of the opening; depositing a conductive material, filling the opening; polishing or etching back the conductive material to form a lower contact electrode 1 and a lower electrode 4 buried in the opening, the lower contact electrode 1 and the lower electrode 4 being formed in one-piece; removing at least a part of the insulation film; etching an exposed portion of the adhesion improving layer 3; oxidizing the exposed portion of the adhesion improving layer 3; and forming a capacitor dielectric film 5 covering the lower electrode 4.
In the case that the lower contact electrode 1 and the lower electrode 4 are thus formed unseparable in one-piece by CMP, a self-oxide film of the adhesion improving layer 3 is used, whereby the excessive etching step for defining the gap is unnecessary. The steps can be simple.
(24) In the semiconductor device fabrication method according to the present invention described in any one of items (18) to (23), a protection film is formed on the upper surface of the lower electrode 4, and an upper electrode 6 covering a sidewall of the lower electrode 4 is formed by depositing a conductive material and anisotropically etching the conductive material with the protection film as a mask.
It is possible that the protection film is provided on the upper surface of the lower electrode 4 in a projected shape through the adhesion improving layer 3, and anisotropic etching is performed with the protection film as a mask to form the upper electrode 6 forming the capacitor as, e.g., a sidewall-like electrode on the sidewall of the lower electrode 4. This is effective especially in a case that because of high integration the etching of the upper electrode 6 is difficult.